Previously, the designs of low drop out (LDO) regulators with low output load/line transients and relatively high PSRRs have had to sacrifice gain/phase margins. Also, this type of regulator design tended to oscillate when operating at or near its dropout voltage if the input/output line parasitic inductance was higher or the output capacitance was lower than some value required for some applications.
Since device modeling is typically not accurate enough to detect the causes of this type of oscillation, they have been difficult to predict with simulations at low or high temperatures even if the regulator is operating at a relatively normal input voltage. Also, under certain conditions, oscillation can be triggered by transient noise, such as a full load transient. For example, bench tests have shown this type of LDO regulator with 2.8V output voltage starts to oscillate if a wire connected to its input pin is long and a full load transient occurs near its dropout voltage (around 3.0V). Further, this type of LDO regulator has been known to start to oscillate at full load transient when the input inductance increased to 70 nH with an output capacitance of 0.7 μF. Similarly, if this output capacitance is increased to 1.0 μF, this type of LDO regulator often starts to oscillate when the input inductance is increased to 90 nH.
Furthermore, since the input/output line inductance and output capacitance are typically related to a particular application that employs an LDO regulator, which can vary significantly from application to application or even from chip package to chip package, previous LDO regulators were prone to oscillation under various conditions.